1. Field of Invention
This invention relates to floating gate memory devices, such as flash memory, and in particular to methods and circuits for repairing over-erased floating gate memory cells.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. Several popular classes of non-volatile memory are based on arrays of floating gate memory transistors that are electrically erasable and programmable.
The act of programming a memory array of floating gate memory transistors in one popular approach involves injecting the floating gate of addressed cells with electrons which causes a negative charge to accumulate in the floating gate and the turn-on threshold of the memory cell to increase. Thus, when programmed, the cells will not turn on, that is, they will remain non-conductive when addressed with read potentials applied to the control gates. The act of erasing a cell having a negatively charged floating gate involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate. For an opposite polarity array, programming involves selectively removing electrons from the addressed cells"" floating gates.
Floating gate memory cells suffer the problem of over-erasure, particularly when erasing involves lowering the threshold by removing electrons from the floating gate. During the erase step, over-erasure occurs if too many electrons are removed from the floating gate leaving a slight positive charge. The positive charge biases the memory cell slightly on, so that a small current may leak through the memory even when it is not addressed. A number of over-erased cells along a given data line can cause an accumulation of leakage current sufficient to cause a false reading.
In addition to causing false readings, when floating gate cells are over-erased, it makes it difficult to successfully reprogram the cells using hot electron programming, particularly with embedded algorithms in the integrated circuits. This difficulty arises because the program current will be large and, due to series resistance, the effective VDS across cell will drop so that the electron injection efficiency will decrease.
Further, because the erase and program operations can affect different cells in a single array differently, floating gate memory designs often include circuitry for verifying the success of the erasing and programming steps. See, for instance, U.S. Pat. No. 4,875,118, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH MEMORY, invented by Jungroth. If the array does not pass erase verify, the entire array is usually re-erased. The re-erase process can aggravate over-erased cells in the array.
One solution to the over-erase problem associated with the erase verification process is disclosed in U.S. Pat. No. 5,414,664, FLASH MEMORY WITH BLOCK ERASE FLAGS FOR OVER-ERASURE PROTECTION, issued to Lin et al. on May 9, 1995, which shows a method and a device where only those blocks which fail the erase verify operation are re-erased. Accordingly, a re-erase of the entire array after each verify operation is not required. This mitigates the over-erase phenomenon, but does not solve it entirely.
Thus, a repair process has been developed to correct over-erased cells. U.S. Pat. No. 5,233,562, entitled METHODS OF REPAIRING FIELD-EFFECT CELLS IN AN ELECTRICALLY ERASABLE AND ELECTRICALLY PROGRAMMABLE MEMORY DEVICE, issued to Ong, et al., describes processes for such repair using so-called drain disturb, source disturb or gate disturb techniques. After each repair in the Ong patent, a time-consuming repair verification operation of the entire array is provided. See, also, U.S. Pat. No. 5,416,738 to Shrivastava for further background information.
Another attempt to solve the over-erase problem is described in U.S. Pat. No. 5,546,340, entitled NON-VOLATILE MEMORY ARRAY WITH OVER-ERASE CORRECTION, issued to Hu et. al. Hu describes a negatively biased substrate. Hu describes bulk correction of over-erased devices within an array. Hu describes bulk correction of an array of over-erased devices as carried forth in a convergence technique which utilizes higher floating gate injection currents.
A low current method of programming flash EEPROMS is described in U.S. Pat. No. 5,487,033, entitled STRUCTURE AND METHOD FOR LOW CURRENT PROGRAMMING OF FLASH EEPROMS, issued to Keeney et. al. Keeney indicates that a control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for Multilevel Flash EEPROM cell applications.
For further discussion of a technique for correction of over-erasure of flash EPROM""s, please refer to U.S. Pat. No. 5,467,306, entitled METHOD OF USING SOURCE BIAS TO INCREASE THRESHOLD VOLTAGES AND/OR TO CORRECT FOR OVER-ERASURE OF FLASH EPROM""s, issued to Kaya, et. al.
For many repair processes in the prior art, soft programs are implemented as bulk operations applied to all erased cells in a particular memory at the same time. Such bulk operation soft programs consume currents that are excessive for low power applications.
Another problem arises during repair (or soft program) processing after the erase cycle because the soft program cycle is applied to all of the erased cells at the same time, without regard to whether a particular bit line has one or more cells that have been over-erased to a defective condition. Defectively over-erased cells can have extremely low threshold voltages after several erase cycles. Bit lines containing such low threshold voltage cells are considered defective because they consume extremely high current during soft programming. Pumping circuits can be used to provide the data line voltage in a soft program cycle. Because of the limited current capability of such pumping circuits, the inefficiencies caused by the loss of current to over-erased cells are exacerbated when the data line voltage is provided by a pumping circuit.
In any case, the repair and repair verification processes are time-consuming.
Therefore, a method and device which repairs over-erased cells in FLASH memory, and other floating gate memory, more quickly and efficiently is needed.
One aspect of the invention provides a method for soft programming successive bit lines in an integrated circuit having floating gate memory cell arrays. The soft programming method is adapted to quickly and efficiently repair over-erased cells. The soft programming is suitable use in an embedded erase algorithm of other erase sequences for integrated circuit flash memory devices and for other floating gate memories disposed in integrated circuits. According to the invention, the soft program voltage is applied, on a bit line by bit line basis, to successive subject bit lines within an integrated circuit memory array. The bit line soft programming method is also referred to herein as the BLISP method.
The BLISP method is accomplished in a floating gate integrated circuit. The integrated circuit includes a first memory array having a plurality of bit lines. The bit lines correspond to floating gate memory cells. The memory cells are configured to be programmed and erased. Each of the cells has a drain, a source, and a control gate. The control gates of the cells are in communication with word lines.
The BLISP method includes maintaining the word lines at a predetermined word line voltage level. The method also includes generating a soft programming pulse having a soft programming voltage level, selecting a selected bit line, and during the maintaining, applying the soft programming voltage level to cells disposed on a subject bit line corresponding to the selected bit line. This basic BLISP method is typically used for memory arrays with zero defective bit lines, in which case, the subject bit line comprises the selected bit line.
In some embodiments, the first memory array includes conforming bit lines and defective bit lines and the BLISP method is adapted to logically replace the defective bit lines. The selecting includes indicating a bit line type corresponding to the selected bit line. The integrated circuit includes a redundancy system including a second memory array and processing resources. The second memory array has redundant bit lines. The processing resources are adapted to perform the indicating. The bit line types include a conforming bit line type and a defective bit line type. In response to indicating the conforming bit line type, the subject bit line comprises the selected bit line. In response to indicating the defective bit line type, the subject bit line comprises a subject redundant bit line. The subject redundant bit line logically replaces the selected bit line.
For the BLISP method adapted to logically replace the defective bit lines, the first memory array can include a plurality of blocks. Each of the blocks has at least one bit line. Prior to the soft programming the method includes erasing cells disposed in conforming bit lines disposed in blocks having set erase flags, and erasing cells disposed in subject redundant bit lines logically replacing defective bit lines disposed in the blocks having set erase flags.
For the BLISP method adapted to logically replace the defective bit lines, the applying can include the redundancy system turning off the selected bit line in response to the indicating of the defective bit line type, so that the soft programming voltage level is not applied to cells disposed on the selected bit line. The applying can also include the redundancy system turning on the subject redundant bit line so that the soft programming voltage level is applied to cells disposed on the subject redundant bit line.
For the BLISP method adapted to logically replace the defective bit lines, the bit lines in the first memory array can have addresses. The redundancy system processing resources can include a redundancy bit line decoding system having a first set of cells and a logic array. Each cell in the first set can store a bit line type indication corresponding to a predetermined bit line address. The indicating can include the decoding system receiving a bit line address input corresponding to the selected bit line. The indicating can also include the logic array comparing the bit line address input with the bit line type indication of the bit line corresponding to the address input. The applying can include responding to the indicating of the defective bit line type by generating a signal to switch off the soft programming pulse for all of the first memory array cells. The signal can also switch on the soft programming pulse for the subject redundant bit line. The applying can also include responding to the indicating of the conforming bit line type by generating a signal to switch on the soft programming pulse to the selected bit line.
For some of the embodiments having a first set of cells, the redundancy bit line decoding system can include an exclusive NOR gate coupled to the bit line address input and the corresponding bit line type indication. The applying can include, responsive to the indicating of the defective bit line type, the corresponding exclusive NOR gate toggling on a coupled redundant bit line enable signal.
In some embodiments, the selected bit lines have corresponding soft programming flags. The method includes, prior to the maintaining, setting the soft program flags for the selected bit lines. For some of the embodiments having soft programming flags, the bit lines in the first memory array have addresses. After the applying, the method includes determining whether the selected bit line address corresponds to a last address. Responsive to the selected bit line address corresponding to the last address, the soft programming flags for the selected bit lines are reset. Responsive to the selected bit line address not corresponding to the last address, the bit line address is incremented and the maintaining, generating, selecting, and applying steps are repeated for a next bit line corresponding to the incremented address.
A second aspect of the invention provides a method for correcting an over-erase condition within a non-volatile memory array. The method includes providing a first non-volatile memory array in an integrated circuit. The array has a plurality of memory cells. Each memory cell comprises a stacked pair of control and floating gates spaced above a channel region interposed between a source and drain region. The memory cells are arranged in bit lines. The method includes selecting a selected bit line. The method also includes applying a first voltage to the control gate, an active current limiter to the source region, a non-positive voltage to the channel region, and a positive second voltage to the drain region of memory cells disposed in a subject bit line corresponding to the selected bit line.
In some embodiments of the second aspect, the subject bit line comprises the selected bit line. In some embodiments, the first voltage is between minus one volt and six volts.
In some embodiments of the second aspect, the first non-volatile memory array includes conforming bit lines and defective bit lines. The selecting includes indicating a bit line type corresponding to the selected bit line. The integrated circuit includes a redundancy system including a second non-volatile memory array having a plurality of memory cells and processing resources. The second non-volatile memory array has redundant bit lines. The processing resources are adapted to perform the indicating. The bit line types include a conforming bit line type and a defective bit line type. In response to indicating the conforming bit line type, the subject bit line comprises the selected bit line. In response to indicating the defective bit line type, the second voltage is not applied to the selected bit line, and the subject bit line includes a subject redundant bit line logically replacing the selected bit line.
A third aspect of the invention provides an integrated circuit capable of implementing the BLISP method. The integrated circuit comprises a first memory array, processing resources, word lines, and a control circuit. The first memory array has floating gate memory cells disposed on bit lines. Each of the cells in the first memory array has a drain, a source, a floating gate, and a control gate. The processing resources are adapted to select selected bit lines for soft programming. The word lines are in communication with the control gates. The control circuit is coupled with the processing resources to apply a soft program to the floating gate memory cells disposed on subject bit lines, the subject bit lines corresponding to selected bit lines.
In some embodiments of the integrated circuit, the subject bit lines comprise the selected bit lines. In some embodiments, the selected bit lines have corresponding soft programming flags; and the control circuit is adapted to set the soft program flags for the selected bit lines prior to the maintaining.
In some embodiments, the integrated circuit includes a state machine circuit. The first memory array is arranged in blocks of memory cells. Each of the blocks has at least one bit line, and a block erase flag corresponding to the block. The state machine circuit and the processing resources are coupled to erase, prior to the soft programming, cells disposed in the subject bit lines disposed in blocks having set erase flags. The state machine circuit is adapted to determine whether the selected bit line address corresponds to a last address after the applying. In response to the selected bit line address corresponding to the last address, the state machine circuit resets the soft programming flags. For some of these embodiments, the integrated circuit includes an address counter. In response to the selected bit line address not corresponding to the last address, the address counter increments the bit line address and causes the integrated circuit to repeat the soft program for a next bit line corresponding to the incremented address.
In some embodiments of the integrated circuit, the control circuit is adapted to maintain the word lines at a predetermined voltage level. The voltage level set on the word lines is between approximately above ground and 0.5 volts. The applying includes applying a soft program pulse to the subject bit lines while maintaining the word line voltage. In some embodiments, the soft programming pulse repairs over-erased cells so that the over-erased cells may be reprogrammed absent a previously applied repair verify operation.
In some embodiments of the integrated circuit, the first memory array includes a plurality of blocks, arranged in rows and columns. Each block includes the bit lines, the word lines, and source lines. The control circuit is coupled to the bit lines, the source lines, and the word lines. The control circuit is adapted to set threshold voltages of the cells in selected blocks to a low threshold voltage. The control circuit includes voltage supply circuits to supply a voltage sequence to lower the threshold voltages of cells in each selected block. The voltage sequence results in a first group of cells having threshold voltages lowered below a selected limit for the threshold voltage. The voltage supply circuits supply a soft programming pulse to subject bit lines disposed in each selected block during a soft programming time interval across the source lines and the bit lines, while setting the voltage on the word lines to a level below the selected limit.
In some embodiments of the integrated circuit, the first memory array is arranged in rows and columns. The integrated circuit includes well lines coupled to wells of respective rows of cells in the first memory array. The control circuit includes voltage supply circuits to supply a well voltage on the well lines corresponding to the selected bit lines. The control circuit couples an active current limiter to the source lines corresponding to the selected bit lines. In some embodiments, the processing resources include a soft program repair state machine and an address counter.
In some embodiments of the integrated circuit, the first memory array bit lines comprise defective bit lines and conforming bit lines. The integrated circuit includes a redundancy system having a second array of floating gate memory cells disposed on redundant bit lines, and processing resources. Each of the cells in the second memory array has a drain, a source, and a control gate. The redundant bit lines logically replace the defective bit lines. The processing resources adapted to indicate bit line types of the selected bit lines in the first memory array are disposed in the redundancy system. The subject bit lines include selected conforming bit lines and subject redundant bit lines logically replacing selected defective bit lines. The control circuit is adapted to cooperate with the redundancy system to prevent applying of the soft program to floating gate memory cells disposed on defective bit lines.
For some of the embodiments of the integrated circuit having a redundancy system, the applying includes applying a soft program pulse. The bit lines in the first memory array have addresses. The redundancy system processing resources include a redundancy bit line decoding system. The redundancy bit line decoding system includes a first set of cells, a logic array, and processing resources. Each cell in the first set of cells stores a bit line type indication corresponding to a predetermined bit line address. The logic array is adapted to compare each bit line address input with the bit line type indication corresponding to the address input. The processing resources are adapted to receive bit line address inputs corresponding to the selected bit lines. The processing resources respond to a defective bit line type indication by generating a signal to switch off the soft programming pulse for the first memory array bit lines. The processing resources respond to a conforming bit line type indication by generating a signal to switch on the soft programming pulse for the selected bit line.
For some of the embodiments of the integrated circuit having a redundancy system, the applying includes applying a soft program pulse. Responsive to an indication of the conforming bit line type, the redundancy system processing resources are adapted to enable application of the soft program pulse to the selected bit lines. Responsive to an indication of the defective bit line type, the processing resources are adapted to disable application of the soft program pulse to the selected bit lines, and enable application of the soft program pulse to the subject redundant bit lines logically replacing the selected bit lines.
For some of the embodiments of the integrated circuit having a redundancy system, the first memory array is arranged in blocks of memory cells. Each of the blocks has at least one bit line, and a block erase flag corresponding to the block. The control circuit and the redundancy system processing resources are coupled to erase, prior to the soft programming, cells disposed in the selected conforming bit lines disposed in blocks having set erase flags. The control circuit and the redundancy system processing resources are also coupled to erase, prior to the soft programming, cells disposed in the subject redundant bit lines logically replacing defective bit lines, the defective bit lines disposed in blocks having set erase flags.
For some of the embodiments of the integrated circuit having a redundancy system, the first memory array and the second memory array are arranged in rows and columns. The integrated circuit includes well lines coupled to wells of respective rows of cells in the first memory array and coupled to respective rows of cells in the second memory array. The control circuit voltage supply circuits supply a well voltage on the well lines corresponding to the selected bit lines. The control circuit couples an active current limiter to the source lines corresponding to the selected bit lines.
For some of the embodiments of the integrated circuit having a redundancy system, the applying includes applying a soft program pulse. The redundancy system processing resources include a redundancy bit line decoding system having a first set of cells. Each cell in the first set stores a bit line type indication corresponding to a predetermined bit line address. The redundancy bit line decoding system also has a logic array. The logic array is adapted to compare each bit line address input with the bit line type indication corresponding to the address input. The redundancy bit line decoding system also has processing resources adapted to receive bit line address inputs corresponding to the selected bit lines.
The redundancy bit line decoding system processing resources are adapted to respond to a defective bit line type indication by generating a signal to switch off the soft programming pulse for the first memory array bit lines, and to switch on the soft programming pulse for the subject redundant bit line. The redundancy bit line decoding system processing resources are adapted to respond to a conforming bit line type indication by generating a signal to switch on the soft programming pulse to the selected bit line. The redundancy bit line decoding system can include exclusive NOR gates coupled to the bit line address inputs and the corresponding bit line type indications. Responsive to defective selected bit line type indications, the exclusive NOR gates are adapted to toggle on the coupled redundant bit line enable signals.
A fourth aspect of the invention provides a floating gate memory comprising floating gate cells, a first circuit, and a second circuit. The floating gate cell have a drain, a control gate, a floating gate, a well, and a source. The floating gate cells are disposed on bit lines in a first memory array. The first circuit is adapted to select selected bit lines. The second circuit is adapted to soft program floating gate cells in subject bit lines. The subject bit lines correspond to the selected bit lines. The second circuit is also adapted to supply a gate voltage to the control gate, an active current limiter to the drain, a well voltage to the well, and a source voltage to the source of the floating gate cells in the subject bit lines.
For some of the embodiments, the memory includes floating gate cells having a drain, a control gate, a floating gate, a well, and a source. The floating gate cells are disposed on bit lines in a second memory array. The second circuit is adapted to supply a gate voltage to the control gate, an active current limiter to the drain, a well voltage to the well, and a source voltage to the source of the cells in the second memory array. The subject floating gate cells are also disposed on redundant bit lines. The redundant bit lines disposed in the second memory array. The redundant bit lines logically replacing defective bit lines in the first memory array.